Description
The RISC-V Instruction Set Manual contains a documented ambiguity for the Machine Trap Vector Base Address (MTVEC) register that may lead to a vulnerability due to the initial state of the register not being defined, potentially leading to information disclosure, data tampering and denial of service.
Published: 2021-08-13
Score: 9.8 Critical
EPSS: < 1% Very Low
KEV: No
Impact: n/a
Action: n/a
AI Analysis

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Remediation

No vendor fix or workaround currently provided.

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Tracking

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Advisories
Source ID Title
EUVD EUVD EUVD-2021-6571 The RISC-V Instruction Set Manual contains a documented ambiguity for the Machine Trap Vector Base Address (MTVEC) register that may lead to a vulnerability due to the initial state of the register not being defined, potentially leading to information disclosure, data tampering and denial of service.
History

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Subscriptions

Risc-v Instruction Set Manual
cve-icon MITRE

Status: PUBLISHED

Assigner: nvidia

Published:

Updated: 2024-08-03T15:55:18.614Z

Reserved: 2020-11-12T00:00:00.000Z

Link: CVE-2021-1104

cve-icon Vulnrichment

No data.

cve-icon NVD

Status : Modified

Published: 2021-08-13T16:15:07.153

Modified: 2024-11-21T05:43:36.313

Link: CVE-2021-1104

cve-icon Redhat

No data.

cve-icon OpenCVE Enrichment

No data.

Weaknesses