Description
In the Linux kernel, the following vulnerability has been resolved:

spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer

While transmitting with rx_len == 0, the RX FIFO is not going to be
emptied in the interrupt handler. A subsequent transfer could then
read crap from the previous transfer out of the RX FIFO into the
start RX buffer. The core provides a register that will empty the RX and
TX FIFOs, so do that before each transfer.
Published: 2024-08-17
Score: 5.5 Medium
EPSS: < 1% Very Low
KEV: No
Impact: n/a
Action: n/a
AI Analysis

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Remediation

No vendor fix or workaround currently provided.

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Tracking

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Advisories
Source ID Title
Ubuntu USN Ubuntu USN USN-7154-1 Linux kernel vulnerabilities
Ubuntu USN Ubuntu USN USN-7155-1 Linux kernel (NVIDIA) vulnerabilities
Ubuntu USN Ubuntu USN USN-7156-1 Linux kernel (GKE) vulnerabilities
Ubuntu USN Ubuntu USN USN-7154-2 Linux kernel (HWE) vulnerabilities
Ubuntu USN Ubuntu USN USN-7196-1 Linux kernel (Azure) vulnerabilities
History

Thu, 02 Oct 2025 18:45:00 +0000

Type Values Removed Values Added
Weaknesses NVD-CWE-noinfo
CPEs cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:*
Metrics cvssV3_1

{'score': 5.8, 'vector': 'CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:U/C:L/I:H/A:L'}

cvssV3_1

{'score': 5.5, 'vector': 'CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:N/A:H'}


Thu, 12 Sep 2024 10:30:00 +0000

Type Values Removed Values Added
Weaknesses CWE-388
Metrics cvssV3_1

{'score': 5.5, 'vector': 'CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:N/A:H'}

cvssV3_1

{'score': 5.8, 'vector': 'CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:U/C:L/I:H/A:L'}


Wed, 11 Sep 2024 13:30:00 +0000

Type Values Removed Values Added
Metrics ssvc

{'options': {'Automatable': 'no', 'Exploitation': 'none', 'Technical Impact': 'partial'}, 'version': '2.0.3'}


Mon, 19 Aug 2024 19:15:00 +0000

Type Values Removed Values Added
References
Metrics threat_severity

None

cvssV3_1

{'score': 5.5, 'vector': 'CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:N/A:H'}

threat_severity

Moderate


Sat, 17 Aug 2024 09:15:00 +0000

Type Values Removed Values Added
Description In the Linux kernel, the following vulnerability has been resolved: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer.
Title spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer
References

Subscriptions

Linux Linux Kernel
cve-icon MITRE

Status: PUBLISHED

Assigner: Linux

Published:

Updated: 2026-05-11T20:29:16.986Z

Reserved: 2024-07-30T07:40:12.261Z

Link: CVE-2024-42279

cve-icon Vulnrichment

Updated: 2024-09-11T12:42:23.809Z

cve-icon NVD

Status : Analyzed

Published: 2024-08-17T09:15:08.880

Modified: 2025-10-02T18:32:28.330

Link: CVE-2024-42279

cve-icon Redhat

Severity : Moderate

Publid Date: 2024-08-17T00:00:00Z

Links: CVE-2024-42279 - Bugzilla

cve-icon OpenCVE Enrichment

Updated: 2025-07-13T11:30:57Z

Weaknesses