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Tracking
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Thu, 05 Feb 2026 15:30:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| First Time appeared |
Chipsalliance rocketchip
|
|
| CPEs | cpe:2.3:a:chipsalliance:rocketchip:*:*:*:*:*:*:*:* | |
| Vendors & Products |
Chipsalliance rocketchip
|
Wed, 12 Nov 2025 21:15:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| Weaknesses | CWE-266 | |
| Metrics |
cvssV3_1
|
Wed, 12 Nov 2025 13:00:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| First Time appeared |
Chipsalliance
Chipsalliance rocket-chip |
|
| Vendors & Products |
Chipsalliance
Chipsalliance rocket-chip |
Mon, 10 Nov 2025 20:15:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| Description | A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability. | |
| References |
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Status: PUBLISHED
Assigner: mitre
Published:
Updated: 2025-11-12T20:39:11.448Z
Reserved: 2025-10-27T00:00:00.000Z
Link: CVE-2025-63384
Updated: 2025-11-12T20:38:58.424Z
Status : Analyzed
Published: 2025-11-10T20:15:49.013
Modified: 2026-02-05T15:25:19.137
Link: CVE-2025-63384
No data.
OpenCVE Enrichment
Updated: 2025-11-12T12:50:00Z